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This macro may seem quite complex, but the actual code it produces is very simple. The macro will work on low-end, mid-range, and PIC18 PIC microcontroller architectures. The basis of the delay code is the three-instruction-cycle loop:

decfsz DlayCount, f goto $ - 1

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Each time this loop executes, three cycles are taken up. To set the initial DlayCount value, the number of cycles to delay is compared against the maximum value possible for a bit value in DlayCount. For example, setting bit 2 of DlayCount will cause the loop code to execute four times. If bit 6 is used, DlayCount will loop 64 times. Instead of dividing the total number by 3 (which is the number of loops required) and then loading the w register with the value (which changes the w register) and then writing to the DlayCount variable, I set the appropriate bit for the count in DlayCount.

This is a bit hard to understand (and pretty hard to see in the macro code above). To try to make the operation more obvious, I want to show some pseudocode that better illustrates how the delay value is calculated. The output of the code is assumed to be the DlayCount variable with the appropriate bits set.

TotalDelay = RequestedDelay; DlayCount = 0; // Final Value to Delay Value = 1 << 7; // Test Value TFlag = 0; for (i = 0; i < 8; i++ ) { // Repeat for all 8 Bits if ((TFlag == 0) && (TotalDelay > (Value * 3))) { DlayCount = DlayCount | Value; // Mark the Correct Bit Value TotalDelay = TotalDelay - (Value * 3); TFlag = 1; // Mark that Value Changes } else if ((TFlag != 0) && (TotalDelay > ((Value * 3) + 1))) { DlayCount = DlayCount | Value; // Mark the Correct Bit Value TotalDelay = TotalDelay - ((Value * 3) + 1); } Value = Value >> 1; // Take down the Division Value }

The reason why one is added to the delay after the rst time through is because of the way the code is produced. The rst time a DlayCount bit is set, the code becomes

bsf DlayCount, Bit decfsz DlayCount, f goto $ - 1

and the delay is simply calculated as 2 to the power of Bit multiplied by 3. Thus, for bit 4 being set, the delay would be

The sampling interval At must be long enough to let the process return to equilibrium after each change in controller output. When At has expired, the most recent AC/AM is calculated and compared to K,: e, = $$ - K, n Next, the output of the controller is stepped proportional to the error signal by a gain K,: Am n+~ = Keen The effect#ive reset time is related inversely to gain and directly to sampling interval At: (6.23) The sampling optimizer is not affected by the same equipment limitations as its continuous counterpart, but its other characteristics are similar. The sampling is of some advantage on processes dominated by dead time, but introduces the same uncertainty factor as other sampling controllers encountered. I\ otice the similarity of the control programs to that of the incremental DDC algorithms. Naturally a DDC computer may be readily programmed with this optimizing function. Sampling, however, still does not permit its use on processes without self-regulation.

Delay = = = = = (2 (1 (1 16 48 ** Bit) * 3 << Bit) * 3 << 4) * 3 * 3

bsf DlayCount, Bit1 bsf DlayCount, Bit2 decfsz DlayCount, f goto $ - 1

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